Comparison of Three Different 2-D Space Vector PWM Algorithms and Their FPGA Implementations
Abstract
To improve the flexibility of the multilevel space vector pulse width modulation (SVPWM), different algorithms have been developed. A theoretical comparison is made for three 2-D SVPWM algorithms: they are 60° g-h coordinate SVPWM (60° SVPWM), 45° rotating coordinate SVPWM (45° SVPWM) and multilevel SVPWM based on two-level algorithm (SVPWM based on two-level). The aim is to provide a guideline for the selection of the most appropriate SVPWM technique for digital implementation. Among them, the 45° SVPWM offers the best flexibility with the least calculation and is well suited for digital implementation. The SVPWM based on two-level is most intuitionistic but with largest calculation. New general methods of the 60° and 45° algorithms for any level SVPWM are also provided, which needs only the angle θ and the modulation depth m to generate and arrange the final vector sequence. All three methods are implemented in a field programmable gate array (FPGA) with very high speed integrated circuit hardware description language (VHDL) and compared in terms of implementation complexity and logic resources required. Simulation results show the absolute advantages of 45° SVPWM in briefness and resources use. Finally, an experimental test result is presented with a three-level neutral-point-clamped (NPC) inverter.References
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[2] J. Rodriguez, J.-S. Lai, and F. Z. Peng, “Multilevel inverters: A survey of topologies, controls, and applications,” IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 724–738, Aug. 2002.
[3] J. Rodriguez, S. Bernet, B. Wu, J. Pontt, and S. Kouro, “Multilevel voltage-source-converter topologies for industrial medium-voltage drives,” IEEE Trans. Ind. Electron., vol. 54, no. 6, pp. 2930–2945, Dec. 2007.
[4] E. P. Wiechmann, P. Aqueveque, R. Burgos, and J. Rodríguez, “On the efficiency of voltage source and current source inverters for high-power drives,” IEEE Trans. Ind. Electron., vol. 55, no. 4, pp. 1771–1782, Apr. 2008.
[5] A. K. Gupta and A. M. Khambadkone, “A space vector PWM scheme for multilevel inverters based on two-level space vector PWM,” IEEE Trans. Ind. Electron., vol. 53, no. 5, pp. 1631–1639, Oct. 2006.
[6] A. R. Beig, G. Narayanan, and V. T. Ranganathan, “Modified SVPWM algorithm for three level VSI with synchronized and symmetrical waveforms,” IEEE Trans. Ind. Electron., vol. 54, no. 1, pp. 486–494, Feb. 2007.
[7] A. K. Gupta and A.M. Khambadkone, “A general space vector PWM algorithm for multilevel inverters, including operation in overmodulation range,” IEEE Trans. Power Electron., vol. 22, no. 2, pp. 517–526, Mar. 2007.
[8] A. Mohamed A. S., A. Gopinath, and M. R.
Baiju, “A simple space vector PWM generation scheme for any general n-level inverter,” IEEE Trans. Ind. Electron., vol. 56, no. 5, pp. 1649–1656, May 2009.
[9] N. Celanovic and D. Boroyevich, “A fast space-vector modulation algorithm for multilevel three-phase converters,” IEEE Trans. Ind. Appl., vol. 37, no. 2, pp. 637–641, Mar./Apr. 2001.
[10] Z. Shu, N. Ding, J. Chen, H. Zhu, and X. He, “Multilevel SVPWM with DC-link capacitor voltage balancing control for diode-clamped multilevel converter based STATCOM,” IEEE Trans. Ind. Electron., vol. 60, no. 5, pp. 1884–1895, May 2013.
[11] J. H. Seo, C. H. Choi, and D. S. Hyun, “A new simplified space–vector PWM method for three-level inverters,” IEEE Trans. Power Electron., vol. 16, no. 4, pp. 545–550, July 2001.
[12] J. J. R. Andina, M. J. Moure, and M. D. Valdes, “Features, design tools, and application domains of FPGAs,” IEEE Trans. Ind. Electron., vol. 54, no. 4, pp. 1810–1823, Aug. 2007.
[13] D. Navarro, O. Lucia, L. A. Barragan, J. I. Artigas, I. Urriza and O. Jimenez, “Synchronous FPGA-based high-resolution implementations of digital pulse-width modulators,” IEEE Trans. Power Electron., vol. 27, no. 5, pp. 2515–2525, MAY 2012.
[14] B. Alecsa, M. N. Cirstea, and A. Onea, “Multi-DSP and -FPGA-Based Fully Digital Control System for Cascaded Multilevel Converters Used in FACTS Applications,” IEEE Trans. Ind. Informat., vol. 8, no. 3, pp. 511–527, Aug. 2012.
[15] B. Alecsa, M. N. Cirstea, and A. Onea, “Simulink modeling and design of an efficient hardware-constrained FPGA-based PMSM speed controller,” IEEE Trans. Ind. Informat., vol. 8, no. 3, pp. 554–562, Aug 2012.
[16] L. Idkhajine, E. Monmasson, and A. Maalouf, “Fully FPGA-based sensorless control for synchronous AC drive using an extended Kalman filter,” IEEE Trans. Ind. Electron., vol. 59, no. 10, pp. 3908–3918, Oct. 2012.
[17] H. F. Blanchette, T. O. Bachir, and J. P. David, “A state-space modeling approach for the FPGA-based real-time simulation of high switching frequency power converters,” IEEE Trans. Ind. Electron., vol. 59, no. 12, pp. 4555–4567, Dec. 2012.
[18] M. P. Aguirre, L. Calvino, and M. I. Valla, “Multilevel current-source inverter with FPGA control,” IEEE Trans. Ind. Electron., vol. 60, no. 1, pp. 3–10, Jan. 2013.
[19] M. Curkovic, K. Jezernik and R. Horvat, “FPGA-based predictive sliding mode controller of a three-phase inverter,” IEEE Trans. Ind. Electron., vol. 60, no. 2, pp. 637–644, Feb. 2013.
[20] P. S. B. Nascimento, H. E. P. d. Souza, F. A. S. Neves, and L. R. Limongi, “FPGA implementation of the generalized delayed signal cancelation—phase locked loop method for detecting harmonic sequence components in three-phase signals,” IEEE Trans. Ind. Electron., vol. 60, no. 2, pp. 645–658, Feb. 2013.
[21] M. Shahbazi, P. Poure, S. Saadate, and M. R. Zolghadri, “Fault-tolerant five-leg converter topology with FPGA-based reconfigurable control,” IEEE Trans. Ind. Electron., vol. 60, no. 6, pp. 5024–5031, Jun. 2013.
[22] K. Jezernik, J. Korelic, and R. Horvat, “PMSM sliding mode FPGA-based control for torque ripple reduction,” IEEE Trans. Power Electron., vol. 28, no. 7, pp. 3549–3556, Jul. 2013.
[23] M. Shahbazi, P. Poure, S. Saadate and M. R. Zolghadri, “FPGA-based reconfigurable control for fault-tolerant back-to-back converter without redundancy,” IEEE Trans. Ind. Electron., vol. 60, no. 8, pp. 3360–3371, Aug. 2013.
[24] Z. Shu, J. Tang, Y. Guo, and J. Lian, “An efficient SVPWM algorithm with low computational overhead for three-phase inverters,” IEEE Trans. Power Electron., vol. 22, no. 5, pp. 1797–1805, Sep. 2007.
[25] G. Oriti and A. L. Julian, “Three-phase VSI with FPGA-based multisampled space vector modulation,” IEEE Trans. Ind. Appl., vol. 47, no. 4, pp. 1813–1820, July/Aug. 2011.
[26] S. Pan, J. Pan, and Z. Tian, “A shifted SVPWM method to control DC-link resonant inverters and its FPGA realization,” IEEE Trans. Ind. Electron., vol. 59, no. 9, pp. 3383–3391, Sep. 2012.
[27] Y. Y. Tzou and H. J. Hsu, “FPGA realization of space-vector PWM Control IC for three-phase PWM inverters,” IEEE Trans. Power Electron., vol. 12, no. 6, pp. 953–963, Nov. 1997.
[28] H. Hu, W. Yao, and Z. Lu, “Design and implementation of three-level space vector PWM IP core for FPGAs,” IEEE Trans. Power Electron., vol. 22, no. 6, pp. 2234–2244, Nov. 2007.
[29] O. López, J. Alvarez, J. Doval-Gandoy, and F. D. Freijedo, “Multilevel multiphase space vector PWM algorithm,” IEEE Trans. Ind. Electron., vol. 55, no. 5, pp. 1933–1942, May 2008.
[30] O. López, J. Alvarez, J. Doval-Gandoy, and F. D. Freijedo, “Multi-level multiphase space vector PWM algorithm with switching state redundancy,” IEEE Trans. Ind. Electron. , vol. 56, no. 3, pp. 792–804, Mar. 2009.
[31] J. Alvarez, O. López, F. D. Freijedo, and J. Doval-Gandoy, “Digital parameterizable VHDL module for multilevel multiphase space vector PWM,” IEEE Trans. Ind. Electron. , vol. 58, no. 9, pp. 3946–3957, Sep. 2011.
[32] O. López, J. Alvarez, J. Doval-Gandoy, and F. D. Freijedo, “Comparison of the FPGA implementation of two multilevel space vector PWM algorithms,” IEEE Trans. Ind. Electron., vol. 55, no. 4, pp. 1537–1547, Apr. 2008.
Published
2014-05-22
How to Cite
FAN, Bishuang; TAN, Guanzheng; FAN, Shaosheng.
Comparison of Three Different 2-D Space Vector PWM Algorithms and Their FPGA Implementations.
Journal of Power Technologies, [S.l.], v. 94, n. 3, p. 176--189, may 2014.
ISSN 2083-4195.
Available at: <https://papers.itc.pw.edu.pl/index.php/JPT/article/view/468>. Date accessed: 21 nov. 2024.
Issue
Section
Electrical Engineering
Keywords
Space vector pulse width modulation (SVPWM), field programmable gate array (FPGA), 60° g-h coordinate, 45° rotating coordiante, multilevel inverter
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